As semiconductor device dimensions are decreased, and device density increases, it becomes more difficult to efficiently and reliably fabricate isolation structures for separating active areas of the device. One common method of forming isolation structures for semiconductor devices is referred to as localized oxidation of silicon (LOCOS). However, the limits of the standard LOCOS process have motivated the development of new isolation processes.
Shallow trench isolation (STI) has become the most common and important isolation technology for sub-quarter micron complementary metal oxide semiconductor (CMOS) devices. Conventional STI processes include corner rounding and divot formation (i.e., oxide recess) along STI edges. In some scenarios, the divot at the edge of the STI is formed due to wet dip of a pad oxide by an HF solution.